Modern integrated circuit designs have become extremely complex. As a result, various techniques have been developed to verify that circuit designs will operate as desired before they are implemented in an expensive manufacturing process. For example, logic simulation is a tool used for verifying the logical correctness of a hardware design. Designing hardware today involves writing a program in the hardware description language. A simulation may be performed by running that program. If the program runs correctly, then one can be reasonably assured that the logic of the design is correct at least for the cases tested in the simulation.
Software-based simulation, however, may be too slow for large complex designs such as SoC (System-on-Chip) designs. The speed of execution of a simulator drops significantly as the design size increases due to cache misses and memory swapping. Emulation and prototyping significantly increase verification productivity by employing reconfigurable hardware modeling devices including emulators and prototyping devices. Field programmable gate arrays (FPGAs)-based emulators and prototyping devices rely on an actual silicon implementation and perform circuit verification generally in parallel as the circuit design will execute in a real device. By contrast, a simulator performs circuit verification by executing the hardware description code serially. The different styles of execution can lead to orders of magnitude differences in execution time.
While reconfigurable hardware modeling device-based emulation and prototyping are much faster than simulation for system-on-chip designs, verifying circuit designs for networking applications at the system level remains a challenge. These designs can reach billion-gate sizes and are complex in various dimensions, imposing a variety of requirements on the verification environment.
A network switch, for example, receives traffic from its ingress pin interfaces and after some traffic arbitration, flow control and routing, sends it out through its egress pin interfaces. These ingress and egress pin interfaces are also known as ports. The port interfaces follow the network protocol in both directions. Hence the verification components that drive traffic into the ports and receive traffic from the ports have to be protocol compliant. A modern-day Ethernet switch can have a large number of such ingress/egress ports (e.g., from 64 to 256). The number is expected to grow up to 1024 in the coming future. All port configurations need to be tested; and the performance and bandwidth of the network switch design need to be checked and measured.
A verification system typically includes a reconfigurable hardware modeling device programmed to implement at least a hardware model of the networking circuit design under test, a traffic generation device configurable to generate traffic mimicking the complexities of real life networking traffic, and a traffic analysis device configurable to qualify and measure a variety of different parameters important for the verification. The traffic generation device may be able to create multiple streams of traffic and then combine them in a desired proportion or scheme to be sent to a given port on the switch design. The packets in a stream may be given different priorities as per the protocol.
The traffic generation device and the traffic analysis device may be implemented by a complex software tool running on a computer. This complex software tool can generate message packets at a speed much faster than the speed at which the hardware model implemented on a reconfigurable hardware modeling device can process message packets. This is at least in part because the traffic generation is a software algorithm operating at a high level of abstraction whereas the hardware model runs the switch design at a low, RTL level of abstraction.
The speed mismatch can complicate verifying performance of a circuit design for a networking device. Latency and bandwidth are two important performance characteristics, defining the speed and capacity of a networking device, respectively. Latency represents a delay for relaying a message, which can be caused by limited processing speed and queuing of the networking device; and bandwidth represents maximum throughput or the amount of data that can be transferred during a second. A good networking device typically is able to deliver high bandwidth and low latency. Determination of these two time-related performance components of a modeled circuit design is thus important for design verification. Different operating speeds, however, makes it difficult for the traffic analysis device to perform it.
A mere replacement of wall-clock time with model time provided in the reconfigurable hardware modeling device as a global time reference cannot solve the problem. The traffic generation device typically runs ahead of the modeled circuit design and thus at any point of time it would have already generated messages to be consumed by the modeled circuit design at a future model time. The situation is reversed for the traffic analysis device, which typically analyzes packets sent out in the past w.r.t. the current model time. Moreover, because of message buffering between the traffic generation/analysis device and the reconfigurable hardware modeling device for flow control, finding a global time reference does not appear to be a viable solution to the speed mismatch problem associated with the latency and bandwidth analysis.